The present invention relates to techniques for providing on-chip termination impedance, and more particularly, to techniques for providing on-chip termination impedance to differential input/output pins.
Integrated circuits have input/output (IO) pins that are used to transmit signals into and out of the circuit. An external termination resistor is usually coupled to each IO pin to provide impedance termination. An impedance termination resistor reduces reflection of input signals on signal lines coupled to the IO pin.
However, external resistors typically use a substantial amount of board space. Therefore, it would be desirable to provide a technique for providing impedance termination for IO pins in an integrated circuit that does not occupy as much board space.
Prior art integrated circuit have provided on-chip termination impedance by coupling a field-effect transistor to an IO pin. The gate voltage of the transistor is controlled by a calibration circuit to regulate the impedance of the on-chip transistor. On-chip transistors have also been applied across differential IO pins to provide impedance termination.
The impedance of on-chip transistors are sensitive to process, voltage, and temperature variations on the integrated circuit. Therefore, it would be desirable to provide on-chip impedance termination that is less sensitive to process, voltage, and temperature variations on an integrated circuit.